1. Field of the Invention
The invention relates to a random access memory (RAM) memory circuit which has a plurality of banks each having a multiplicity of memory cells and further contains an auxiliary device for testing. A preferred, but not exclusive, field of the invention is dynamic RAM memory circuits (DRAMs).
2. Description of the Related Art
The acronym “RAM” (derived from “Random Access Memory”) is usually used to designate a data memory having a multiplicity of memory cells, each of which can store a datum and which can be accessed selectively and directly to selectively write in or read out data. In many cases, the memory cells are combined in a plurality of separate cell arrays, so-called “banks”. Each of these banks has a dedicated cell selection device containing a network of switchable data paths and a network of selection control lines for controlling the switching functions in the data path network.
The selection device of a bank can be activated by a bank address and, in the activated state, responds to a cell address information item applied to select the memory cells identified (“addressed”) thereby for a write or read operation. This selection is effected, in principle, by the selection device exciting selected selection control lines depending on the cell address information item to actuate assigned switches in the data path network and thereby to switch through data transfer paths between the addressed memory cells and a data bus assigned to the relevant bank (“bank bus”).
On account of this selection process, write data, which are provided on the bank bus when a write command appears, finds their way into the addressed memory cells, and when a read command appears, the data contained in the addressed memory cells finds their way to the bank bus. The bank bus is typically a parallel bus for simultaneously transferring n data (or n bits), and the selection device is designed such that a group of n memory cells can in each case be addressed simultaneously and selected for writing or reading by means of one cell address information item. The bank buses can usually be connected selectively, depending on the bank address, via a bank multiplexer to a bidirectional data port containing n parallel data transfer channels which, for their part, are connected to n external data terminals of the memory circuit for the purpose of receiving and transmitting the data to be written in or read out.
To check the functionality of a RAM memory circuit, various tests are necessary at various stages of production. Such tests consist, in principle, in writing a specific datum in each case to each memory cell and, during subsequent read accesses, checking whether the data read out correspond to the data previously written in. Memory tests are typically carried out with the aid of external test units which operate according to a selectable test program to provide the respective address and data information items for the selection of the memory cells and for the data to be written in. Additionally, the external test units supply command bits for prescribing the respective operating mode of the memory circuit and generate strobe signals for interrogating the test results.
Ever larger storage densities result in ever longer test times per memory circuit. Since the test time is a significant cost factor, efforts are made to shorten it. A known contribution to shortening the test time consists in both the bank buses and the selection devices of all the banks being switched in parallel during the writing-in of the test data, so that each group of n write data is simultaneously written to the respectively addressed memory cell group of all the banks. A parallel operation of the bank buses cannot be carried out in read operation, however, because the read data from different banks would then be superposed on one another, so that errors cannot be discriminated.
Therefore, the prior art has been restricted to shortening the duration of the read operation by bridging the customary waiting times which have to be complied with between successive accesses to different memory cell groups in a bank. Specifically, before each new read access in a given bank, it is necessary to wait until the data-carrying lines in the selection device are brought to their mutual charging state again. To usefully bridge these waiting times, it is known to address the individual banks in a time-interleaved manner during read-out in such a way that, immediately after reading has been effected at one bank (i.e., before the waiting time has actually lapsed at said bank), another bank is accessed. However, this enables only a few percent of the total memory read-out time to be saved.